The present invention relates to a MOS semiconductor device having a substrate voltage-generating circuit.
In a semiconductor substrate in which a large number of semiconductor elements, especially MOS semiconductor elements, are formed, the potential of the semiconductor substrate is generally maintained at a predetermined value to ensure stable operation of the semiconductor elements. In order to maintain the potential of the substrate at a predetermined value, an external voltage may be applied to the substrate. However, in such a case, it is necessary to provide an extra terminal pin. Therefore, in many cases an integrated circuit (IC) has a substrate voltage-generating circuit therein.
The above-mentioned substrate voltage-generating circuit, illustrated in FIG. 1, is a typical example of a prior art substrate voltage-generating circuit. In FIG. 1, 1 indicates an oscillating circuit and 2 indicates a pumping circuit. The oscillating circuit 1 has an oscillator 11, a waveform shaping circuit 12, and an output-stage circuit 13. The waveform shaping circuit 12 comprises the MOS transistors Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4, the output-stage circuits 13 comprises the MOS transistors Q.sub.5 and Q.sub.6, and the pumping circuit 2 comprises a MOS capacitor Q.sub.7 and the MOS transistors Q.sub.8, Q.sub.9.
In the substrate voltage-generating circuit of FIG. 1, a rectangular waveform signal S1, alternating between "H" and "L" levels, which is generated by the oscillator 11 is input into the wave-form shaping circuit 12. In the waveform shaping circuit 12, the MOS transistors Q.sub.1 and Q.sub.2 form a first inverter and the MOS transistors Q.sub.3 and Q.sub.4 form a second inverter. The signal S1 from the oscillator 11 is shaped and inverted by the first inverter. The output signal S2 of the first inverter is input into the second inverter and is inverted by it. The output signal S2 of the first inverter is also input to the gate of the MOS transistor Q.sub.6 of the output-stage circuit 13, and the output signal S3 of the second inverter is input to the gate of the MOS transistor Q.sub.5 of the output-stage circuit 13.
Since the signal S3 is the inverted signal of the signal S2, the MOS transistors Q.sub.5 and Q.sub.6 are turned ON and OFF in turn. When the transistor Q.sub.5 is turned ON and the transistor Q.sub.6 is turned OFF, the potential V.sub.N1 of the node N.sub.1 is pushed up by the cpacitance of the MOS capacitor Q.sub.7 ; however, the potential V.sub.N1 is clamped near the threshold voltage V.sub.th of the MOS transistor Q.sub.8 because the transistor Q.sub.8 is turned ON when the potential V.sub.N1 increases at the level of V.sub.th. In this condition, when the transistor Q.sub.5 is turned OFF and the transistor Q.sub.6 is turned ON, the gate voltage V.sub.G of the MOS capacitor Q.sub.7 is changed from "H" level to "L" level. Then the potential V.sub.N1 of the node N.sub.1 is decreased by the capacitance of the MOS capacitor Q.sub.7 and becomes lower than the substrate voltage V.sub.BB. The MOS transistor Q.sub. 9, which is connected as a diode, is turned ON, and the electric charge in the substrate is drawn out through the MOS transistor Q.sub.9 into the capacitance of the MOS capacitor Q.sub.7.
The above-mentioned pumping operation of the pumping circuit 2 is illustrated in FIG. 2. In FIG. 2, the waveforms of the voltages V.sub.G, V.sub.N1, and V.sub.BB are illustrated. As described above, according to the substrate voltage-generating circuit of FIG. 1, the electric charge in the substrate is drawn out through the pumping capacitor Q.sub.7 to the ground terminal V.sub.SS so the substrate potential V.sub.BB is set at a predetermined negative value.
A sectional view of the semiconductor device comprising the substrate voltage-generating circuit of FIG. 1 is illustrated in FIG. 3. In FIG. 3, 3 indicates a p-type semiconductor substrate. On the substrate 3, the MOS capacitor Q.sub.7, the node N.sub.1, the MOS transistor Q.sub.9, and the output terminal T.sub.a are formed. The node N.sub.1 and the terminal T.sub.a are formed as N.sup.+ -type diffusion layers. A wiring line L.sub.1 is provided for connecting the gate of the MOS transistor Q.sub.9 to the node N.sub.1 and another wiring line L.sub.2 is provided for connecting the node N.sub.1 to the substrate 3.
The above-mentioned substrate voltage-generating circuit of FIG. 1 is incorporated into the semiconductor substrate 3 on which the semiconductor device is formed, and accordingly the output voltage V.sub.BB of the substrate voltage-generating circuit of FIG. 1 has a fixed relation to the voltage source V.sub.CC fed to the semiconductor device. The above-mentioned semiconductor device must be operated normally in the predetermined range of the voltage source V.sub.CC and in the predetermined range of the substrate voltage V.sub.BB. The above-mentioned normal operation area on the V.sub.CC -V.sub.BB plane is shown as C.sub.1 in FIG. 4. In FIG. 4, V.sub.CC0 indicates the standard value of the voltage source V.sub.CC, i.e. 5.0 V, and V.sub.BB0 indicates the standard value of the substrate voltage V.sub.BB, i.e. -3.0 V.
Each chip of the semiconductor device which has been manufactured according to a normal process is expected to have a normal operation area shown as C.sub.1 in FIG. 4. However, some faulty semiconductor device may have such a normal operation area as shown as C.sub.3 or C.sub.4 in FIG. 4. Such a semiconductor device with an abnormal margin for the substrate voltage should be detected by means of the wafer-probing test and removed.
In order to determine whether a semiconductor device has an abnormal margin, it is necessary to test the semiconductor device on some operation points inside the normal operation area C.sub.1, such as P.sub.1, P.sub.2, P.sub.3 and P.sub.4. However, in the semiconductor device comprising the substrate voltage-generating circuit of FIG. 1, the substrate voltage V.sub.BB, i.e. the output voltage of the above-mentioned circuit, has a relation to the voltage source V.sub.CC as shown as C.sub.2 in FIG. 4. Accordingly, in the above-mentioned semiconductor device, such operation points as P.sub.1 and P.sub.3 can not be realized.
In order to realize such operation points as P.sub.1 and P.sub.3 in the above-mentioned semiconductor device, it is necessary to apply an external voltage to the terminal T.sub.a so as to force the substrate voltage to change. However, applying an external voltage to the terminal T.sub.a may cause some difficulty. That is, if the substrate voltage V.sub.BB is forced to change to near ground level by the external voltage in order to realize the operation point P.sub.1, the voltage V.sub.N1 of the node N.sub.1 becomes substantially negative to the substrate voltage V.sub.BB because in such a condition the substrate voltage-generating circuit is still operating. Accordingly, the PN junction formed by the node N.sub.1 and the substrate 3 as shown in FIG. 3 is supplied with a forward voltage so that a large forward current flows through the above-mentioned PN junction, and a large number of electrons are injected from the node N.sub.1 into the substrate 3. These injected electrons may be introduced into the channels of the MOS transistors, thereby interfering with the normal operation of the semiconductor device.
In the semiconductor device comprising the substrate voltage-generating circuit of FIG. 1, a problem exists as described above, in that the margin test for the voltage source V.sub.CC and the substrate voltage V.sub.BB can not be effected exactly.